Field of the Invention
The invention relates to an integrated circuit configuration for driving a field-effect-controllable power semiconductor component with a load on the source side. A control circuit connected between a gate terminal and a source terminal of the power semiconductor component drives the gate with a gate potential that is higher than its drain terminal. The control circuit is integrated in a well of a first conductivity type, the well is embedded in a zone of a semiconductor body of a second conductivity type, and the zone is connected to the drain terminal of the power semiconductor component. A parasitic diode in the control circuit is formed by a p-n junction between the well and the zone. The parasitic diode is disposed between the drain and the source of the power semiconductor component.
Such circuit configurations are a component of so-called "smart FETs". Smart FETs are commercially available and their specifications and layout can be found in the relevant data specifications. The basic layout of such a circuit configuration is shown in FIG. 4, and its basic integration is shown in FIG. 5. The problem the present invention seeks to solve will now explained with reference to these drawing figures.
With reference to FIG. 4, the power semiconductor component is a power MOSFET 1. A load 2 is connected in series with it on the source side, and a generator 3 is connected parallel to the load. The series circuit comprising 1, 2 and 3 is connected to an operating voltage V.sub.bb such that the drain terminal D is at the potential V.sub.bb.
In order for them to be turned on, power MOSFETs with a load on the source side are known to require a gate potential that is higher than the drain potential. This potential is generated for instance by a charge pump 7, which is part of an integrated control circuit 4 used to drive the power MOSFET 1. Since the reference potential for the control circuit is generally ground, the charge pump 7 must generate a voltage that is higher than the voltage V.sub.bb. The gate-to-source voltage U.sub.GS of 1 is generally limited, between the gate terminal G and the source terminal S, by at least one Zener diode 8. The control circuit 4 has a control input with the terminals 5, 6. By applying an input voltage U.sub.in to the terminals 5, 6, the charge pump 7 is put into operation, and the power MOSFET 1 is rendered conducting.
When an on-board electrical system in a motor vehicle, for instance, is in operation, then the generator 3 typically generates a current for the load 2 and for charging the battery to the operating voltage V.sub.bb The voltage generated by the generator must therefore be higher than V.sub.. The battery can be charged, however, only if the power MOSFET 1 remains in the conducting state. Charging with the parasitic diode that is connected antiparallel to the power MOSFET 1 is not desired, because that would lead to major losses because of the high threshold voltage. On the other hand, it is then not assured that the power MOSFET 1 will remain in the on state with the aid of the charge pump 7 of the integrated circuit configuration 4. This is so because the integrated control circuit 4 also has at least one parasitic diode, identified by reference numeral 9. This diode is connected to the source terminal of the power MOSFET 1 via one output of the control circuit, and to the drain terminal of the power MOSFET via a supply voltage terminal of the control circuit.
If in generator operation the source potential becomes greater than the drain potential, then the parasitic diode 9 begins to conduct. It switches on a parasitic bipolar transistor, which is connected between the drain terminal G and the drain terminal D of the power MOSFET 1. Turning on the parasitic bipolar transistor prevents the gate potential from becoming greater than the drain potential. Accordingly, in the generator mode, the power MOSFET 1 cannot be turned on.
FIG. 5 shows the integrated version of the control circuit of FIG. 4. A p-doped well 12 is embedded in a weakly n-doped semiconductor body 11, and a highly n-doped zone 17 is in turn embedded in the well 12. The zone 17 forms the cathode zone of the protective diode 8, while the parasitic diode 9 is formed by the p-doped well 12 and the n-doped zone 11. The zone 17, analogously to the circuit of FIG. 4, is connected via a contact to the output of the charge pump 7 and to the gate terminal of the power MOSFET 1. The power MOSFET 1 is typically integrated into the same semiconductor body, and has a p-doped base zone 14 and source zones 15 embedded in the base zone 14. The zones 14 and 15 are contacted and, via a contact, are connected with the well 12. The well 12 is thus at the source potential. If the generator is not in operation, the drain potential of the MOSFET 1 is thus blocked, as the parasitic bipolar transistor 13 is formed by the zones 17, 12 and 11. In the generator mode, as noted, the source potential is higher than the drain potential, and the parasitic diode 9 is thus conducting and the parasitic bipolar transistor 13 is on. A current thus flows between the zone 17 and the zone 11, or in other words between the charge pump 7 and the terminal V.sub.bb. The voltage at the gate of the power MOSFET 1 therefore drops, and the power MOSFET can no longer be turned on.
An integrated circuit configuration of this generic type for driving a power MOSFET with a load on the source side is known from the commonly owned German patent DE 44 29 285. There, a power MOSFET with a source terminal and a drain terminal is disclosed which is driven via a control circuit. That circuit configuration also has a parasitic diode in the control circuit.
To avoid the parasitic diode, or in other words to isolate it, a p-n isolation is typically used, of the kind described by Contiero et al. in "Design of a High Side Driver in Multipower BCD and VIPower Technologies": Electron Devices, Washington, December 1987, IEEE, pp. 766-769. There, for p-n isolation, an antiseries diode is connected between the control electronics and the drain region.